TSB12LV21BPGF

Product Summary

The TSB12LV21BPGF is an IEEE 1394 link layer controller which provides a high-performance IEEE 1394-1995 interface with the capability to transfer data between the 1394 PHY-link interface, the PCI bus interface, and external devices connected to the local bus interface. The 1394 PHY-link interface provides the connection to the 1394 physical layer device; it is supported by the onboard link layer controller (LLC). The LLC provides the control for transmitting and receiving 1394 packet data between the FIFO and PHY-link interface at rates of 100 Mbit/s, 200 Mbit/s, and 400 Mbit/s. The TSB12LV21BPGF provides the capability to receive status from the physical layer device and to access the physical layer control and status registers by the application software.

Parametrics

TSB12LV21BPGF absolute maximum ratings: (1)Supply voltage range: VCC –0.5 V to 4 V, VCCP –0.5 V to 6 V, VCC5V –0.5 V to 6 V; (2)Input voltage range for Universal PCI, VI: PCI: –0.5 V to VCCP + 0.5 V; (3)Input voltage range for 5-V tolerant TTL/LVCMOS, VI: –0.5 V to VCC5V + 0.5 V; (4)Output voltage range for Universal PCI, VO: –0.5 V to VCCP + 0.5 V; (5)Output voltage range for 5-V tolerant TTL/LVCMOS, VO: –0.5 V to VCC5V + 0.5 V; (6)Input clamp current, IIK (VI < 0 or VI > VCC): ± 20 mA; (7)Output clamp current, IOK (VO < 0 or VO > VCC): ± 20 mA.

Features

TSB12LV21BPGF features: (1)IEEE Standard for 1394-1995 Compliant; (2)IEEE Standard for 1212-1991 Compliant; (3)Supports IEEE 1394-1995 Link Layer Control; (4)PCI Local Bus Specification Rev. 2.1N Compliant; (5)Supports IEEE 1394 Transfer Rates of 100, 200, and 400 Mb per Second; (6)3.3-V Core Logic While Maintaining 5-V Tolerant Inputs; (7)Performs the Function of 1394 Cycle Master; (8)Provides 4K Bytes of Configurable FIFO RAM; (9)Provides Five Scatter-Gather DMA Channels; (10)Provides Software Control of Interrupt Events; (11)Provides Four General-Purpose Input/Outputs; (12)Supports Plug-and-Play (PnP) Specification; (13)Generates 32-bit CRC for Transmission of 1394 Packets; (14)Performs 32-bit CRC Checking on Reception of 1394 Packets; (15)Provides PCI Bus Master Function for Supporting DMA Operations; (16)Provides PCI Slave Function for Read/Write Access of Internal Registers; (17)Supports Distributed DMA Transfers Between 1394 and Local Bus RAM, ROM, AUX, or Zoomed Video; (18)Advanced Submicron, Low-Power CMOS Technology; (19)Packaged in a 176-Pin PQFP (PGF).

Diagrams