AD9779BSVZRL

Product Summary

The AD9779BSVZRL is a dual, 12-/14-/16-bit, high dynamic range, digital-to-analog converter (DAC) that provides a sample rate of 1 GSPS, permitting multicarrier generation up to the Nyquist frequency. The AD9779BSVZRL includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The AD9779BSVZRL is manufactured on an advanced 0.18 μm CMOS process and operate on 1.8 V and 3.3 V supplies for a total power consumption of 1.0 W. They are enclosed in 100-lead TQFP packages. The applications of the AD9779BSVZRL include Wireless infrastructure, WCDMA, CDMA2000, TD-SCDMA, WiMax, GSM Digital high or low IF synthesis, Internal digital upconversion capability, Transmit diversity and Wideband communications: LMDS/MMDS, point-to-point.

Parametrics

AD9779BSVZRL absolute maximum ratings: (1)AVDD33, DVDD33 AGND,DGND,CGND: -0.3 V to +3.6 V; (2)DVDD18, CVDD18 AGND,DGND,CGND: -0.3 V to +1.98 V; (3)AGND DGND,CGND: -0.3 V to +0.3 V; (4)DGND AGND,CGND: -0.3 V to +0.3 V; (5)CGND AGND, DGND: -0.3 V to +0.3 V; (6)I120, VREF, IPTAT AGND ?0.3 V to AVDD33 + 0.3 V; (7)IOUT1-P, IOUT1-N, IOUT2-P, IOUT2-N, Aux1-P, Aux1-N, Aux2-P, Aux2-N, AGND: -1.0 V to AVDD33 + 0.3 ; (8)P1D15 to P1D0, P2D15 to P2D0, DGND: -0.3 V to DVDD33 + 0.3 V; (9)DATACLK, TXENABLE, DGND: -0.3 V to DVDD33 + 0.3 V; (10)CLK+, CLK, CGND: -0.3 V to CVDD18 + 0.3 V; (11)RESET, IRQ, PLL_LOCK, SYNC_O+, SYNC_O-, SYNC_I+, SYNC_I-, CSB, SCLK, SDIO, SDO, DGND: -0.3 V to DVDD33 + 0.3 V; (12)Junction Temperature: +125℃; (13)Storage Temperature Range: -65 to +150℃.

Features

AD9779BSVZRL features: (1)Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS, full operating conditions; (2)SFDR = 78 dBc to fOUT = 100 MHz; (3)Single carrier WCDMA ACLR = 79 dBc @ 80 MHz IF; (4)Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω ; (5)Novel 2×, 4×, and 8× interpolator/coarse complex modulator allows carrier placement anywhere in DAC bandwidth; (6)Auxiliary DACs allow control of external VGA and offset control ; (7)Multiple chip synchronization interface; (8)High performance, low noise PLL clock multiplier; (9)Digital inverse sinc filter; (10)100-lead, exposed paddle TQFP package.

Diagrams