(Hong Kong)
Product Summary
The MC10EP51DR2 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip.flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the MC10EP51DR2 allow the device to be used as a negative edge triggered flip-flop. The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEE and the CLK input will be biased at VCC/2.
Parametrics
MC10EP51DR2 absolute maximum ratings: (1)VCC PECL Mode Power Supply VEE = 0 V: 6 V; (2)VEE NECL Mode Power Supply VCC = 0 V: -6 V; (3)VI PECL Mode Input Voltage VEE = 0 V VI ≤ VCC: 6V; (4)NECL Mode Input Voltage VCC = 0 V VI ≥ VEE: -6V; (5)Iout Output Current Continuous: 50mA; (6)Iout Output Current Surge: 100mA; (7)IBB VBB Sink/Source: ± 0.5 mA; (8)TA Operating Temperature Range: -40 to +85 ℃; (9)Tstg Storage Temperature Range: -65 to +150 ℃; (10)θJA Thermal Resistance (Junction to Ambient): 0 lfpm 190℃/W, 500 lfpm 130℃/W; (11)θJC Thermal Resistance (Junction to Case): 41 to 44 ± 5% ℃/W; (12)Tsol Solder Temperature (<2 to 3 Seconds: 245℃ desired): 265℃.
Features
MC10EP51DR2 features: (1)350 ps Typical Propagation Delay; (2)Maximum Frequency > 3 GHz Typical; (3)PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V; (4)NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V; (5)Open Input Default State; (6)Safety Clamp on Inputs; (7)Pb-Free Packages are Available.
Diagrams
| Image | Part No | Mfg | Description |  |
Pricing (USD) |
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 MC10EP51DR2 |
ON Semiconductor |
Flip Flops 3.3V/5V ECL D-Type |
Data Sheet |
Negotiable |
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MC10EP51DR2G |
ON Semiconductor |
Flip Flops 3.3V/5V ECL D-Type w/Reset and Diff Clk |
Data Sheet |
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