XC2C64A-7VQG44C

Product Summary

The XC2C64A-7VQG44C is a CoolRunner-II 64-macrocell CPLD that is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved. The XC2C64A-7VQG44C consists of four Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, the XC2C64A-7VQG44C can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain, and programmable grounds. A Schmitt trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers can be configured as "direct input" registers to store signals directly from input pins.

Parametrics

XC2C64A-7VQG44C absolute maximum ratings: (1)VCC Supply voltage relative to ground: –0.5 to 2.0 V; (2)VCCIO Supply voltage for output drivers: –0.5 to 4.0 V; (3)VJTAG JTAG input voltage limits: –0.5 to 4.0 V; (4)VCCAUX JTAG input supply voltage –0.5 to 4.0 V; (5)VIN Input voltage relative to ground: –0.5 to 4.0 V; (6)VTS Voltage applied to 3-state output: –0.5 to 4.0 V; (7)VSTG Storage Temperature (ambient): –65 to +150℃; (8)TJ Junction Temperature: +150℃.

Features

XC2C64A-7VQG44C features: (1)Optimized for 1.8V systems; (2)Industry’s best 0.18 micron CMOS CPLD; (3)Available in multiple package: 44-pin VQFP with 33 user I/Os; (4)Fastest in system programming: 1.8V ISP using IEEE 1532 (JTAG) interface; (5)IEEE1149.1 JTAG Boundary Scan Test; (6)Optional Schmitt-trigger input (per pin); (7)Two separate I/O banks; (8)RealDigital 100% CMOS product term generation; (9)Flexible clocking modes: Optional DualEDGE triggered registers; (10)Global signal options with macrocell control: Multiple global clocks with phase selection per macrocell, Multiple global output enables, Global set/reset; (11)Efficient control term clocks, output enables, and set/resets for each macrocell and shared across function blocks; (12)Advanced design security; (13)Optional bus-hold, 3-state, or weak pullup on selected I/O pins; (14)Open-drain output option for Wired-OR and LED drive; (15)Optional configurable grounds on unused I/Os; (16)Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels; (17)PLA architecture: Superior pinout retention, 100% product term routability across function block; (18)Hot pluggable.

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