Product Summary

The EPM7064AETC100-7N is a high-density, high performance Programmable Logic device which based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EPM7064AETC100-7N operates with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz.

Parametrics

EPM7064AETC100-7N absolute maximum ratings: (1)Supply voltage With respect to ground: –0.5 to 4.6 V; (2)DC input voltage: –2.0 to 5.75 V; (3)DC output current, per pin: –25 to 25 mA; (4)Storage temperature No bias: –65 to 150 ℃; (5)Ambient temperature Under bias: –65 to 135 ℃; (6)Junction temperature BGA, FineLine BGA, PQFP, and packages, under bias: 135 ℃.

Features

EPM7064AETC100-7N features: (1)Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1; (2)Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71; (3)Enhanced ISP features: Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices), ISP_Done bit to ensure complete programming (excluding; (4)EPM7128A and EPM7256A devices), Pull-up resistor on I/O pins during in-system programming; (5)Pin-compatible with the popular 5.0-V MAX 7000S devices; (6)High-density PLDs ranging from 600 to 10,000 usable gates; (7)Extended temperature range.

Diagrams

EPM7064AETC100-7N block diagram

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