TMS320C30GEL

Product Summary

The TMS320C30GEL is a digital signal processor. The TMS320C30GEL is the newest member of the TMS320C3x generation of DSPs from Texas Instruments (TIE). The TMS320C30GEL is a 32-bit floating-point processor manufactured in 0.7-mm triple-level-metal CMOS technology. The device’s internal busing and special DSP instruction set have the speed and flexibility to execute up to 50 MFLOPS (million floating-point operations per second). The TMS320C30GEL optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.

Parametrics

TMS320C30GEL absolute maximum ratings: (1)Supply voltage range, VCC: -0.3 V to 7 V; (2)Input voltage range, VI: -0.3 V to 7 V; (3)Output voltage range, VO: -0.3 V to 7 V; (4)Continuous power dissipation: 3.15 W; (5)Operating case temperature range, TC: 0℃ to 85℃; (6)Storage temperature range, Tstg: -55℃ to 150℃.

Features

TMS320C30GEL features: (1)High-Performance Floating-Point Digital Signal Processor (DSP); (2)32-Bit High-Performance CPU; (3)16-/32-Bit Integer and 32-/40-Bit Floating-Point Operations; (4)32-Bit Instruction Word, 24-Bit Addresses; (5)Two 1K × 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks; (6)One 4K × 32-Bit Single-Cycle Dual-Access On-Chip ROM Block; (7)On-Chip Memory-Mapped Peripherals: Two Serial Ports; Two 32-Bit Timers; One-Channel Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation; (8)Two 32-Bit External Ports; (9)24- and 13-Bit Addresses; (10)0.7-mm Enhanced Performance Implanted CMOS (EPICE) Technology; (11)208-Pin Plastic Quad Flat Package (PPM Suffix); (12)181-Pin Grid Array Ceramic Package (GEL Suffix); (13)Eight Extended-Precision Registers; (14)Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs); (15)Two- and Three-Operand Instructions; (16)Parallel Arithmetic and Logic Unit (ALU) and Multiplier Execution in a Single Cycle; (17)Block-Repeat Capability; (18)Zero-Overhead Loops With Single-Cycle Branches; (19)Conditional Calls and Returns; (20)Interlocked Instructions for Multiprocessing Support; (21)Two Sets of Memory Strobes (STRB and MSTRB) and One I/O Strobe (IOSTRB); (22)Separate Bus-Control Registers for Each Strobe-Control Wait-State Generation.

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