TMS320C31PQA50

Product Summary

The TMS320C31PQA50 is a 32-bit, floating-point processor, manufactured in 0.6 mm triple-level-metal CMOS technology. The TMS320C31PQA50 is a part of the TMS320C3x generation of DSPs from Texas Instruments. The TMS320C31PQA50’s internal busing and special digital-signal-processing instruction set have the speed and flexibility to execute up to 80 million floating-point operations per second (MFLOPS). The device optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.

Parametrics

TMS320C31PQA50 absolute maximum ratings: (1)Supply voltage range, VDD: -0.3 V to 7 V; (2)Input voltage range, VI: -0.3 V to 7 V; (3)Output voltage range, VO: -0.3 V to 7 V; (4)Continuous power dissipation (worst case): 2.6 W; (5)Operating case temperature range, TC PQL (commercial): 0℃ to 85℃; PQA (industrial): -40℃ to 125℃; (6)Storage temperature range, Tstg: -55℃ to 150℃.

Features

TMS320C31PQA50 features: (1)High-Performance Floating-Point Digital Signal Processor (DSP): 40-ns Instruction Cycle Time 275 MOPS, 50 MFLOPS, 25 MIPS; (2)32-Bit High-Performance CPU; (3)16-/32-Bit Integer and 32-/40-Bit Floating-Point Operations; (4)32-Bit Instruction Word, 24-Bit Addresses; (5)Two 1K × 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks; (6)Boot-Program Loader; (7)On-Chip Memory-Mapped Peripherals: One Serial Port; Two 32-Bit Timers; One-Channel Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation; (8)Fabricated Using 0.6 mm Enhanced Performance Implanted CMOS (EPICE) Technology by Texas Instruments (TIE); (9)132-Pin Plastic Quad Flat Package (PQ Suffix); (10)Eight Extended-Precision Registers; (11)Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs); (12)Two Low-Power Modes; (13)Two- and Three-Operand Instructions; (14)Parallel Arithmetic/Logic Unit (ALU) and Multiplier Execution in a Single Cycle; (15)Block-Repeat Capability; (16)Zero-Overhead Loops With Single-Cycle Branches; (17)Conditional Calls and Returns; (18)Interlocked Instructions for Multiprocessing Support; (19) Bus-Control Registers Configure Strobe-Control Wait-State Generation.

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